1. Field of the Invention
This invention relates to electronic systems, and more particularly, circuitry for addressing memory devices in electronic systems.
2. Description of the Related Art
Memories such as cache memories include a plurality of cells arranged in an array. The cells may be connected to each other by bitlines and wordlines. One embodiment of an array of cells in a cache memory is shown in FIG. 1. As shown in the drawing, the cells are connected in rows by wordlines and connected in columns by pairs of bitlines. Each bitline of a plurality of cells may convey a signal that is a logical complement with respect to the signal carried on the other bitline of the pair (which may be referred to as an inverse bitline). Sense amplifiers may be coupled to the bitlines in order to amplify and transmit signals received therefrom.
With the advent of smaller feature sizes in current microprocessors (and other types of integrated circuits), the trend towards lower operating voltages, and the increases in operating speed (i.e. clock frequencies), the traditional arrangement shown above may not always be suitable. Variations in parameters such as temperature, voltage, or process may introduce biases into the bitlines (and corresponding Sense Amplifiers), wherein the sense amplifiers are more prone to read one logic value over another logic value. These biases, in the absence of compensation, may cause erroneous values to be read from the memory cells.
One solution to the problems described above is to use a plurality of local bitlines coupled to a global bitline (sometimes referred to as a ‘domino’ approach). FIG. 2 illustrates one embodiment of such an arrangement for a single bitline of a bitline pair. In the embodiment shown, a group of cells are connected to local bitline, which is in turn coupled to a global bitline. The plurality of bitlines may be coupled to the global bitline via a wired-OR approach, or as shown herein, via a sense amplifier. However, even this approach may suffer some of the same drawbacks as the previous approach with the aforementioned advent of smaller feature sizes, lower operating voltages, and increases in operating speed. Thus, these circuit designs may be inadequate for newer microprocessors or other circuits which implement memory circuits as shown in FIG. 1.